The present invention relates to field programmable gate arrays (FPGAs), and more specifically, to FPGAs resistant to soft errors.
FPGAs are programmable devices that are customizable by users to program particular logic into the FPGAs. FPGAs are composed of configurable logic blocks (CLBs) connected by an interconnect structure and surrounded by configurable I/O blocks (IOBs). Each CLB may include configuration memory cells to control the functions performed by the CLB. The configuration memory cells may include lookup tables (LUTs), or truth tables implementing combinational logic.
In memory circuits, including FPGAs, soft errors affect memory when one or more energetic particles bombard one or more transistors to switch on the transistor for a short period of time. In addition, the energetic particles may change a stored value. When a soft error occurs in configuration logic, the logical operation performed by the configuration logic may be changed.